1. Field of the Invention
The present invention relates to a serial data transfer apparatus that converts parallel data to serial data to transfer it. More particularly, the present invention relates to a serial data transfer apparatus provided with a transfer clock generator having an interval control function of a transfer clock used for transferring the data.
2. Description of Related Art
FIG. 1 is a schematic diagram indicating the state where the serial data transfer apparatuses are connected to each other.
In FIG. 1, reference numeral 1 designates a serial data transfer apparatus at the transmit side, and numeral 2 designates a serial data transfer apparatus at the receiving side. In transferring data, clock pulses TCLK are sent from the serial data transfer apparatus 1 at the transmit side to the serial data transfer apparatus at the receiving side. In synchronism with each transfer clock pulse TCLK, each bit composing the data to be transferred (hereinafter, the data to be transferred to the serial data transfer apparatus 2 at the receiving side from the serial data transfer apparatus 1 at the transmit side is called transfer data TD) is transferred successively.
FIG. 2 is a block diagram showing a whole configuration of an example of the serial data transfer apparatus 1.
In FIG. 2, reference numeral 4 designates a transfer clock generator, to which reference clock pulses CLK generated in a clock generator (not shown) are inputted for generating the transfer clock pulses TCLK. Numeral 5 designates a shifter, which transmits parallel data as serial data, in that it outputs the data to be transferred bit by bit while shifting it, in synchronism with the transfer clock pulses TCLK generated by the transfer clock generator 4.
In FIG. 3, essential parts for the transfer clock interval function in the conventional serial data transfer apparatus, that is, a configuration example of the transfer clock generator 4 shown in FIG. 2 is shown.
In addition, the transfer clock interval means the number of clock pulses of frequency dividing clock DCLK during the period between the time after a unit of data is transferred and the time when the next unit of data is transferred.
In FIG. 3, reference numeral 6 designates a frequency divider which inputs the reference clock pulses CLK to divide the frequency of them so as to generate the frequency dividing clock pulses DCLK. The reference clock pulses CLK are generated by a clock generator (not shown). The frequency dividing clock pulses DCLK generated by the frequency divider 6 are supplied to a transfer clock output circuit 11, a counter 7, and a transfer interval timer 9.
The counter 7 counts the frequency dividing clock pulses DCLK, and when the count value reaches a predetermined number, it outputs a count finish signal CF to the transfer interval timer 9.
The transfer interval timer 9 is composed, more specifically, of a reload register 12 and a counter 13. The count finish signal CF outputted from the counter 7 is inputted to the reload register 12 and the frequency dividing clock pulses DCLK outputted from the frequency divider 6 are inputted to the counter 13.
The counter 13 of the transfer interval timer 9 counts the transfer interval of the transfer clock pulses TCLK by counting the frequency dividing clock pulses DCLK. Specifically, the counter 13 of the transfer interval timer 9 is configurated as a down counter, and the reload register 12 loads, when given the transfer interval count start signal CS from the counter 7, a reload value RV held in advance to the counter 13. Then the counter 13 of the transfer interval timer 9 counts down with the reload value RV as an initial value, and gives the count value CV2 to a decoder 22.
The decoder 22 decodes the count value CV2 given from the counter 13 of the transfer interval timer 9, and when the count value CV2 reaches a value of one clock pulse before the last count value, that is, "1", the decoder 22 outputs an output enable signal EN which is fed to the transfer clock output circuit 11 and the counter 7.
The transfer clock output circuit 11 outputs the transfer clock pulses TCLK in accordance with the frequency dividing clock pulses DCLK fed from the frequency divider 6 when the output enable signal EN becomes enabled.
In addition, when the output enable signal EN outputted from the decoder 22 is enabled, the counter 7 performs a counting operation.
Next, explanation will be made of the interval control of the transfer clock pulses according to the configuration shown in the aforementioned FIG. 3, referring to timing charts in FIGS. 4(a) to 4(e) and FIGS. 5(a) to 5(e).
In the timing charts in FIGS. 4(a) to 4(e) and FIGS. 5(a) to 5(e), reference character DCLK shows the waveform of the frequency dividing clock pulses DCLK, CV1 the count value of the frequency dividing clock pulses DCLK by the counter 7, CV2 the count value of the frequency dividing clock pulses DCLK by the counter 13 of transfer interval circuit 9, TCLK the waveform of the transfer clock pulses and TD the transfer data, respectively.
Here, it is assumed that the transfer data TD is 2.sup.n bits, the counter 7 a 2.sup.n base counter of length n-bits and the counter 13 of the transfer interval timer 9, a 2.sup.m base counter of length m-bits and is given the reload value from the reload register 12 to which setting of the reload value RV is variable. In this case, when the transfer interval value of the transfer clock pulses TCLK, that is, the reload value RV to be loaded to the counter 13 from the reload register 12 is assumed to be "x", the counting by the counter 13 of the transfer interval timer 9 is finished after the number of (x+1) clock pulses.
In the following, explanation will be made with the assumption that the counter 7 is an 8-clock counter of length 3 bits, and the counter 13 of the transfer interval timer 9 is a down counter.
At first, explanation will be made on the case where the transfer interval is "2", referring to the timing charts in FIGS. 4(a) to 4(e).
Counting of the frequency dividing clock pulses DCLK is started by the counter 7, and the transfer clock pulses TCLK are outputted from the transfer clock output circuit 11. Since the counting of the counter 7 counts from "0" and finishes at "7", the count finish signal CF, indicating the count finish, is outputted from the counter 7 to the transfer interval timer 9.
In the transfer interval timer 9, when the count finish signal CF is inputted to the reload register 12, "2" is loaded as a reload value to the counter 13 from the reload register 12. Thereby, the counter 13 starts counting the transfer interval value from the next clock pulse of the frequency dividing clock pulses DCLK.
In this case, the count value CV2 of the counter 13 of the transfer interval timer 9 is counted down from "2" to "0", and these values are always given to the decoder 22. The decoder 22 always decodes the count value CV2 of the counter 13 of the transfer interval timer 9. When the count value becomes "1", the decoder detects the fact, and makes the output enable signal EN become enabled.
By the fact that the output enable signal EN is enabled, the counter 7 starts counting from the next clock pulse of the frequency dividing clock pulses DCLK, and the transfer clock output circuit 11 starts outputting the transfer clock pulse TCLK.
In the same way, referring to the timing charts in FIGS. 5(a) to 5(e), explanation will be made on the case where the transfer clock pulses TCLK are outputted continuously.
At first, the counter 7 counts the frequency dividing clock pulses DCLK. When it is finished, the output enable signal EN, indicating the count finish, is outputted to the transfer interval timer 9.
In the transfer interval timer 9, when the count finish signal CF is inputted to the reload register 12, "0" is loaded as a reload value RV to the counter 13 from the reload register 12. This enables the counter 13 to start counting the transfer interval value from the next clock pulse of the frequency dividing clock pulses DCLK.
In this case, since the count value CV2 of the counter 13 of the transfer interval timer 9 is counted down from "0", the transfer clock output circuit 11 immediately has to output the next clock pulse of the transfer clock pulses TCLK. However, since the decoder 22 is so constructed as to detect that the count value CV2 of the transfer counter 13 is "1" to make the output enable signal EN become enabled, it cannot realize the transfer clock cycle of such a transfer interval "0".
The conventional serial data transfer apparatus is so constructed, as above, that the count value CV2 of the counter 13 of the transfer interval timer 9 is detected one clock pulse before the count finish so as to start outputting of the next clock pulse of the transfer clock pulses TCLK. Therefore, it has been impossible to make the interval of the transfer clock pulses TCLK "0", that is, to make the transfer clock pulses TCLK output continuously. In order to realize the continuous output of the transfer clock pulses TCLK, means for judging whether "0" is set or not as the transfer interval and extra control means for the case may be prepared, but this causes new problems such as an increase of the hardware quantity and the like.